A Novel Spin Based Logic Circuitry Synthesis Using SS Gate

Abstract

Because of its perceived advantages, reversible logic has attracted a lot of study attention. It introduces commendable characteristics like low power consumption, minimized garbage output, and least propagation delay. Reversible logic integrated circuits (ICs) have been produced utilizing traditional CMOS topology in a number of published research endeavors up to this point. However, because CMOS technology is already experiencing a common scaling down issue, researchers are now focusing on post-CMOS devices for the manufacturing of reversible integrated circuits in the future. This particular research project is focused on related research projects that feature reversible IC design based on Spintronic. The authors first implemented spin-oriented conventional reversible logic gates and evaluated their effectiveness in terms of generated garbage values, power consumption, device integrity, and size. Later, in order to understand the benefits of the suggested Single Spin Logic based SS gate, the authors come across an SS gate that is singular in its kind and stick to its spin realization.

Introduction

I. INTRODUCTION

Embryonically, Reversible Logic [12] geared exclusive curiosity in terms of Low Dimensional Structures (LDS). The promising esteems of reversible circuitry corroborates the notion of loss less information processing [17, 22, 29, 30-31], low power consumption, low power dissipation, high speed computing and least garbage value generation. Counting on these integrities Researchers strove Feynman, Double Feynman, Toffoli, Fredkin, Peres gates [15] and so on. To pace up with robust [18] technologies Researchers concurrently initialized several subsets such as multiplier [3] using Peres gate, adder [14] using DKG gate, binary to gray converter [10] using Feynman gate, ALU [33] using Feynman, Peres and Fredkin gate and so on. The goodliness of reversible topology [16] was soon benchmarked with its traditional counterpart. One imperative precondition is the elimination of garbage value. This in particular reduces the heat dissipation and power consumption. The quantum cost is an annexed feature of reversible logic which is largely pondered over. Categorically reversible logic circuitry is now enormously scaled to foster future ready computational ICs [19-21, 23-28], RAM, ROM, ASICs and FPGAs. Nonetheless the reversible circuits are comprised of CMOS composite materials and being indebted to intrinsic limitations of CMOS technology, the MOSFET reversible circuitry suffers the pitfall of scaling limitations. But contemporary research articles exhibit countless strives to ratify the scaling limitations of CMOS [5].

Spintronics is one such post CMOS versatile technology that discourse the obscurities of CMOS scaling. It preserves both intrinsic spin of electron and its conjoined magnetic momentum keeping aside the elementary charge of an electron. It indeed exercise maneuvering electron in metal, semiconductors and in heterostructures. Thus spin positioned information processing incorporates a stipulated technology to inject, store, control and manipulate information with the span of spin degree of freedom. Several spin based device proposal fortified spin based circuit realizations and logicalizations including Single Spin Logic (SSL) [32]. These elements mark the dawn of spintronics era.

The authors here realized reversible logic circuitry under the daybreak of SSL and subsequently ventured into a new paradigm of SSL reversible circuitry. Erstwhile the authors have reported such SSL reversible circuitry. In furtherance to such pain sticking endeavor here the authors put forward few noteworthy SSL reversible logicalizations and subsequently tender SSL SS gate and confer its modus operandi.

Accordingly, the authors adhere to SSL SS gate based Half adder and Full adder and outline the attributes of the modeled combinational circuits in terms of garbage value, power consumption, device integrity, robustness, heat dissipation and eventually the ‘no requirement’ of interconnections.

II. THE ORTHOGONALITY OF SPIN REVERSIBLE LOGICALIZATION

The intrinsic spin of an electron steadfast two spin set i.e. spin up ‘↑’ and spin down ‘↓’. This two existing non-degenerate orthogonal spin state are ultimately parallel and anti-parallel to the magnetic field and mutually they encode classical bit ‘1’ and ‘0’. The closest adjoining spin exchange information endowing a three phase clock is fed in unidirectional to the signal flow from input to output. This favors spintronics from conventional physical charge based devices and profoundly dissipates low or no heat even at higher processing speed. The spin degree of freedom in associations to spin interaction is customized for encoding qubit in quantum logic gates. This covalent structure enthuse SSL which detects and controls spin degree of freedom exchange amid ferromagnetic metallic or ferromagnetic semiconductor hetero-structures. Robustly SSL expanded plentifully to be seized in a quantum dot and substantial research has been reported so far to marshal spin in a low magnetic field. SSL based NAND gates (Agarwal et.al), Full Adder (S. Shukla et.al.), Multiplexer (T.K. Bhattacharyya) are designed beforehand [7]. To attain akin pinnacles authors here implement SSL know-how in BJN Gate [9], TR Gate [4], R Gate [2], MUX Gate [13], New Gate [1], NFT Gate [11] and SS Gate [6].

III. ARTICULATION OF SSL IN REVERSIBLE LOGIC DOMAIN

Spin composed electronic research quantized information processing in nano devices. Prior to this work the authors have proposed SSL based Reversible logic circuits as demonstrated in [8]. Authors here chronologically report the novel architectures of SSL synthesized other few notable Reversible Logic Gates (RLG) in which green arrow indicates the input and blue arrow provides the output.

A. BJN Gate

Fig. 1 is the SSL realization of 3×3 BJN gate with three inputs (A, B, C) and three outputs given by P=A, Q=B, R= (A+B) Å C, respectively. It’s quantum cost is 5 and the Garbage Value is limited to zero.

Conclusion

The authors earlier analytically studied the approximation of SSL in the reversible vicinity. This particular research endeavor is a frame work to deliberate the notion of SSL in variety of reversible circuitry and above all the proposed SS gate is realized using SSL to perpetuate the heterogeneity of spin degree of freedom. The linearity of such model is bestowed upon the physiognomies of spin structure in ferromagnetic metal as well as in ferromagnetic semiconductor. The inheritance of such circuits is vested upon the users’ proficiency in improvising spin in the nano region. Moreover, the comparative analysis postulate all benevolence of spin technology uninterruptedly and uncompromisingly. Thus the authors adhere to such reversible logic invention using spin topology and anticipate to maximize its incorporation for future elegant solution of the dead end of CMOS. Lastly the authors acknowledge this specific research maneuver as a fascinating but challenging series of action.

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Copyright

Copyright © 2023 Shantanu Bhadra, Jayanta Aich, Suparna Karmakar, Somnath Dey, Sanjay Bhadra, Soumyendu Banerjee. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.