Adders implemented on VLSI for high-speed ALU

Abstract

This study focuses on the development of high-speed adder circuits utilising the Hardware Description Language (HDL) within the Xilinx ISE 9.2i platform, as well as their implementation on Field Programmable Gate Arrays (FPGAs) to analyse planning parameters. The main building component of the Arithmetic Logic Unit (ALU) is the adder, and hence the performance of the Control Processing Unit is determined by it (CPU). The ALU and the register file are the two primary components of processors. The carry-chain extra operation could be one of the important channels within an ALU. In this paper, we\\\'ve simulated and synthesised a variety of adders in order to find the most efficient one.

Introduction

I. INTRODUCTION

The digit?l ?om?uter LU is a branch of l?gi? design with the goal of developing ap?r??ri?te ?lg?rithms in order to achieve the most efficient use of the available hardw?re. Only a relatively small and precise set of Boolean operations and arithmetic can be performed by the hardware.

Operations are based on a hier?chy of operations that are developed utilising alg?rithms against the hardware. Because, ultimately, speed, power, and LU utilisation are the most commonly cited measures of an algorithm's efficiency.

A. What is an Adder

In  digit?l  ele?tr?ni?s,  ?dder  is  ?  digit?l  ?ir?uit  th?t ?erf?rms  ?dditi?n  ?f  tw?  numbers. m?ny  ??m?uters  ?nd  ?ther  kinds  ?f  ?r??ess?rs,  ?dders  ?re used  n?t  ?nly  in  the  ?LU(s),  but  ?ls?  in  ?ther  ??rts  ?f  the ?r??ess?r,  where  they  ?re  used  t?  ??l?ul?te  ?ddresses,  t?ble indi?es,  ?nd  m?ny  m?re.

??nsider  tw?  bin?ry  v?ri?bles  x  ?nd  y. The bin?ry  sum  is  den?ted  by  x  +  y,  su?h  th?t

0+0=0  0+1=1  1+0=1  1+1=10. Here,  the  result  in  the  l?st  ??se  is  ?  bin?ry  10  (i.e.,  2  in  b?se 10).  The  sum  ?f  tw?  numbers  ??n  be  ?ut  ?f  the  r?nge  ?f  the digits  in  bin?ry  set.  This,  ?f  ??urse,  is  the  ?rigin  ?f  the ??n?e?t  ?f  ?  ??rry  ?ut.  In  the  bin?ry  sum  1+1,  the  result  10 is  viewed  ?s  ?  0  with  ?  1  shifted  t?  the  left  t?  give  ?  “??rry?ut  is  1”.

1. Half Adder: ?  H?lf  ?dder  (H?)  is  ?  l?gi??l  ?ir?uit  th?t  ?erf?rms  ?n ?dditi?n  ??er?ti?n  ?n  tw?  bin?ry  digits.  The  h?lf  ?dder ?r?du?es  ?  sum  ?nd  ?  ??rry  v?lue  whi?h  ?re  b?th  bin?ry digits.  The Boolean equation and Truth table of half adder: S = A XOR B ; C = A AND B 

2. Full Adder: ?  Full  ?dder  (F?)  is  ?  l?gi??l  ?ir?uit  th?t  ?erf?rms  ?n ?dditi?n  ??er?ti?n  ?n  three  bin?ry  digits.  The  full  ?dder ?r?du?es  ?  sum  ?nd  ?  ??rry  v?lue,  whi?h  ?re  b?th  bin?ry digits. ?  F?  ?dds  bin?ry  numbers  ?nd  ????unts  f?r  v?lues  ??rried in  ?s  well  ?s  ?ut.  ?  ?ne-bit  full  ?dder  ?dds  three  ?ne-bit numbers,  ?ften  written  ?s  ?,  B,  ?nd  ?i  here  ?,  B  ?re  the ??er?nds,  ?nd  ?i is  ?  bit  ??rried  in.  The  ?ir?uit  ?r?du?es  ?  tw?-bit  ?ut?ut  sum ty?i??lly  re?resented  by  the  sign?ls  ??(??rry)  ?nd  S(Sum). The  B??le?n  equ?ti?n  ?nd  truth  t?ble: S = A XOR B XOR Ci ; Co = (A AND B) OR (B AND Ci ) OR (Ci AND A)

B. Complex Adders

The  referen?e  t?  eve  ?f  ?dding  single  bits,  let?s  extend  it  t? ?dding  bin?ry  w?rds.  In  gener?l,  ?dding  tw?  n-bit  w?rds yields  ?n  n-bit  sum  ?nd  ?  ??rry-?ut  bit  ?n.  The  ??rry  is ??rried  fr?m  l?wer  bit  ?dder  t?  higher  bit  ?dder.  B?sed  ?n ??rry  tr?nsfer  fr?m  LSB  t?  MSB,  the  ?dders  ?re  ?l?ssified.

1. Ripple Carry Adder: “It  is  ??ssible  t?  ?re?te  ?  l?gi??l  ?ir?uit  using  multi?le  full ?dders  t?  ?dd  N-bit  numbers.”  E??h  full  ?dder  in?uts  ?  ??rry ?in  whi?h  is  the  ??ut  ?f  the  ?revi?us  ?dder.  This  kind  ?f ?dder  is  ?  Ri??le  ??rry  ?dder  (R??)  in,  sin?e  e??h ??rry  bit  "ri??les"  t?  the  next  full  ?dder.

2. Carry-Look Ahead Ladder: “??rry-L??k ?he?d  ?dder is  designed  t? ?ver??me  the  l?ten?y  intr?du?ed  by  the  re?elling  effe?t  ?f the  ??rry  bits  in  R??.”  The im?r?ves  s?eed  by redu?ing  the  ?m?unt  ?f  time  required  t?  determine  ??rry bits.  ??rry  l??k?he?d  l?gi?  uses  the  ??n?e?ts  ?f  gener?ting (G) ?nd ?r???g?ting(?)c

II. PROPOSED METHODOLOGY

A. The Alternate Approaches for Designing of High-Speed Adders(HSA) are Discussed:

1. Carry Skip Adder: The ??rry-skip adder is meant to speed up a long adder by adding the ?r???g?ti?n ?f ??rry bit round a ??rti?n ?f the whole adder. The concept is illustrated in the context of a four-bit adder. The carry-in bit is designated as I and the adder itself generates a carry-out bit of i+4. Two l?gi? g?tes make up the ??rry skipping circuitry. The ND gate recognises the carry-in bit and compares it to the group ?r???g?te sign?ls.P(i,i+3) = Pi+3. Pi+2.Pi+1.P

2. Carry Select Adders: ??rry  Sele?t  ?dders  (?S?)  use  multi?le  n?rr?w ?dders  t?  ?re?te  f?st  wide  ?dders.  ??nsider  the  ?dditi?n  ?f tw?  n  bit  numbers  with  ?  =  ?n-1…..?0  ?nd  b  =  bn-1…..b0.  ?t the  bit  level  the  ?dder  del?y  in?re?ses  fr?m  the  le?st signifi??nt  0th  ??siti?n  u?w?rd,  with  the  (n-1)th  requiringthe  m?st  ??m?lex  l?gi?.  ?  ??rry  sele?t  ?dder  bre?ks  the ?dditi?n  ?r?blem  int?  sm?ller  gr?u?s.  ?  ??rry-sele?t  ?dder ?r?vides  tw?  se??r?te  ?dders  f?r  the  u??er  w?rds,  ?ne  f?r e??h  ??ssibility.  ?  multi?lexer  (MUX)  is  then  used  t? sele?t  the  v?lid  result.

3. Carry Save Adder: Carry – save adder is based on the idea that a complete adder really has three inputs and produces two outputs, as shown. While it is most commonly used to associate the third input with a carry in, it might also be used as a "regular" value. The complete ?dder is utilised as a 3:2 redu?tion network, where it starts with bits from 3-bit words, adds them, and then outputs a 2-bit wide output. Using n separate adders, an n-bit ??rry s?ve ?dder may be constructed. The word ??rry-s?ve comes from the fact that we s?ve the ??rry ?ut w?rds instead of using them right away to calculate the final sum. When we need to add more than two numbers, carry-save adders come in handy. Because the design is generated automatically avoids the delay in the carry-out bits.

III. RESULT AND DISCUSSION

The  design  ?f  high  s?eed  ?dders  is  ne?ess?ry  t?  in?re?se  the ??m?ut?ti?n  s?eed  ?f  ?LU  ?nd  it  su???rts  t?  the  design  ?f high  s?eed  ?r??ess?r.  In  this  rese?r?h,  the  h?rdw?re im?lement?ti?n  ?f  v?ri?us  ?dders  h?s  been  d?ne  t?  ?n?lyze the  s?eed  ?nd  ?re?.  And the following data has been interpreted

16-bit adders: “The total time delay for ripple carry adder, carry-look ahead adder, carry-skip adder and carry-select adder was approximately 21.6 ns, 21.6 ns, 16.6 ns, 23.1 ns respectively.”

8-bit adders: “The total time delay for ripple carry adder, carry-look ahead adder, carry-skip adder and carry-select adder was approximately 13.2 ns, 13.2 ns, 11.5 ns, 15.9 ns respectively.”

Conclusion

The rese?r?h ?rti?le des?ribes ?b?ut the h?rdw?re im?lement?ti?n ?f high s?eed ?dders. In this ???er, the v?ri?us ?dders like full ?dder, ri??le ??rry ?dder, ??rry-l??k ?he?d ?dder, ??rry-ski? ?dder ?nd ??rry –sele?t ?dder h?ve been simul?ted ?nd synthesized. Fin?lly, the ???tured ??r?meters like s?eed ?nd ?re? ?re ??m??red f?r 8 –bit ?nd 16-bit ?dders. This ???er ??n?ludes th?t the ??rry-ski? ?dder is the most effi?ient ?dder in s?eed ?nd ?re? ??nsum?ti?n.

References

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Copyright

Copyright © 2022 Meeth Jain, KB Ramesh. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.