Design and Implementation of 1-bit Full Subtractor Using FinFET

Abstract

A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder\'s design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the inputs. This means Cout is set when any two or more of the three inputs are high (logical 1). Full subtractors are fundamental components in the construction of arithmetic logic units (ALUs), binary adders, and other computational circuits in digital systems, enabling the handling of multi-bit binary addition by cascading multiple full adders.

Introduction

I. INTRODUCTION

The increasing demand for portable, battery-powered devices such as laptops, wristwatches, mobile phones, calculators, and Internet of Things (IoT) gadgets has made power consumption in digital electronic circuits a significant concern. In modern very largescale integration (VLSI) applications, like microprocessors and digital signal processors (DSPs), arithmetic operations such as addition and subtraction are fundamental.

These operations rely heavily on adders and subtractors, which are essential components in digital systems. Full adders and subtractors play a crucial role in the architecture of DSPs and microprocessors. Efficient implementation of Arithmetic Logic Units (ALUs) and floating-point units, which utilize full adders and subtractors, is vital for executing specialized algorithms, especially in low and ultra-low voltage systems.

This paper the full subtractors are designed in various techniques and technologies. The project is aiming to analyse the delay and power characteristics of 10T full subtractor in different techniques and technologies. Finally, we conclude that which is the best design for applications.

II. LITERATURE SURVEY

1. Pakniyat et al. (2018) proposed “Design of High performance and Low Power 16T Full Adder Cells for Subthreshold Voltage Technology”. This paper focused about two new structures of 1–bit full adder circuits suitable for sub-threshold voltage. Comparison has been carried out for propagation delays, power dissipations, PDP, and EDP in sub threshold regime
2. Kumar and Baghel (2017) proposed a paper on “energy efficient single-bit hybrid full adder circuit” for ultra low voltage applications. In this work, a 1-bit full adder (FA) circuit is designed by employing CMOS based XNOR modules and Pass Transistor Logic (PTL) logic for sum and carry generations.
3.  Mehr et al. (2006) presented a paper on “Novel power efficient 12T full Adder”. The proposed adder is operated at 1 volt supply with power consumption of 1.894 µW at 90 nm technology
4. Vijayakumar et al. (2019) outlined the leakage currents in SRAM circuits for low voltage applications. From that research it has been observed that the maximum effort lay on binary arithmetic circuits with less number of transistors.

III. AIM, OBJECTIVES, AND ADDITIVE CIRCUIT

A. Aim

The main aim of the project is to reduce power and delay and compare the design parameters of various transistor technologies of full subtractors.

B. Objectives

The objectives of the project are

1. To Desigd and implement efficient full subtractor using 10T FinFET technology in Cadence Virtuoso tool.
2. Measurement of parameters of the designed full subtractor in FinFET technology.
3. Measurement of parameters of the designed full subtractor with (20,14,10) Transistor Technology.
4. comparison of results of the measured parameters of designed and simulated full subtractor.

C. Subtrctive Circuit:

The Subtractive circuit that we are using to the project is 10T FINFET full subtractor. FINFET stands for Fin Field-Effect Transistor which is a type of 3D Transistor used in modern semiconductor devices for improved performance and lower power consumption. FINFETs have better control over the channel, reducing short-channel effects that are common in traditional MOSFETs.

IV. SOFTWARE USED

Cadence Virtuoso is a prominent Electronic Design Automation (EDA) solutions provider, offering a comprehensive suite of tools for analog, mixed signal and integrated circuit (IC) design. It provides a suite of tools and features that enable us to process the design from initial schematic capture to final layout and verification.

The Key features of Cadence Virtuoso are Schematic Capture, Layout Editor, Simulation and Analysis, Design and Rue Checking, Physical Verification, Parametric Analysis and Custom Design.

The Advantages of Cadence are:

1. Miniaturuzation
2. Powerful routing tools
3. Advanced process node support
4. Customization and Automatiom
5. Extensive verification and validation.

VIII. FUTURE SCOPE

The future scope of a 1-bit full subtractor using FinFET technology is promising due to the various advantages FinFETs offer over traditional MOSFETs.  here are some key areas where this technology could have a significant impact :

1. Speed and Power efficiency
2. Leakage Reduction
3. High-Performance Computing
4. Quantum and Neuromorphic Computing
5. Miniaturization

Conclusion

From the results it is clear that the 10T one-bit full subtractor (FinFET) consume less power and less delay compared to 20Transistor, 14Transistor, 10Transistors with CMOS technology, the proposed 10T, 14T, and 20T OBFS digital system have been used to implement a divider circuit. 10T full subtractor have low power consumption and low delay so it is used for low power applications.

References

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Copyright

Copyright © 2024 M. Vinay, S. Ajay Kumar, M. Sarath Chandra. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.