Design and Simulation of Vedic Multiplier Using Verilog HDL

Abstract

This Paper is created for the simulation of a high speed Vedic multiplier. In the proposed paper, the multiplier circuit is designed by using algorithms that involve Vedic Mathematics. Calculations that involve Vedic mathematics are derived from the old contexts known as Vedas. The VHDL programs are synthesized and simulated using Xilinx ISE simulator. The study of Vedic multipliers is done in comparison with the conventional multipliers to find the fact that which multiplier is fast and efficient and the research and analysis has shown that the Vedic multiplier is more efficient than conventional multipliers because of its fast response in digital signal processing and it gives less delay in system logic design. Vedic mathematics used in the Vedic multiplier increases the speed of multiplier as it reduces the number of partial products. Hence, the speed of the overall digital design can be increased by implementing a Vedic multiplier.

Introduction

I. INTRODUCTION

Multipliers are a major part of DSP algorithms that are used in various fields including computer applications and digital system designing. Multiplication is the most fundamental function in an arithmetic operation. Operations that involve multiplications are slower than addition and subtraction hence it is advised to implement a multiplier that performs fast multiplications to increase the speed of the calculation as fast multiplications result in fast calculations. A high-speed multiplier is needed in system and logical design because it decreases the processors time in DSP algorithms and algorithms involving FET. The need for fast multipliers has become significantly important because the computing applications of the computer is expanding day by day. Vedic multiplier is a fast, convenient and logical way of performing calculations that uses Vedic mathematics derived from the ancient contexts known as 'Vedas'. It minimizes the processors time by reducing the number of delays and partial products. Vedic multiplier is preferred over conventional multipliers as it produces minimum number of partial products while performing multiplication operation.

II. METHODOLOGY

The project is implemented using the following tools and software:

1. XILINX ISE SIMULATOR
2. VERILOG HDL
3. URDHVA- TIRYAKBHYAM SUTRA

Algorithm-

• Flowchart of NxN Vedic Multiplier Multiplier :

Conclusion

1) This implementation is carried out on Spartan-6 board, and the results are displayed on the LCD of the Spartan-6 The Xilinx software has been an effective tool in the modelling of 2x2, 4x4 and 8x8 multipliers based on the principles of Vedic Mathematics, specifically the Urdhvatiryakbhyam sutra. . The multiplier designs are implemented using digital circuits consisting of half adder and full adder circuits. 2) The implementation of vedic multiplier circuits has resulted in fast calculations by decreasing the processors time and delay. The given review paper is an outline of 2x2 and 4x4 vedic multiplier implementation which further lays down the outline of other NxN multipliers. 3) The proposed model of 2-bit and 4-bit and Vedic multiplier uses logic gates and carry adders, resulting in fast response , memory usage, and logic levels when compared to other conventional multipliers. The design is implemented using a carry select adder for performing the calculation of partial products This vedic multiplier simulation is used for fast multiplications in computer, DSP and FFT applications. 4) The 8-bit Vedic multiplier architecture uses logic gates and carry adders. Together latency, memory usage and logic levels are reduced when compared to the drag coefficient designs.

References

[1] Jagadguru Swami Sri Bharati Krishna Tirthji Maharaja authored \"Vedic Mathematics,\",lndia, in 1986. [2] A multiplier design in ancient Indian Vedic mathematics was presented by Honey Durga Tiwari, Ganzorig Gankhuyag, Chan MO Kim, and Yong Beom Cho from the Department of Electronics Engineering at Konkuk University in Seoul, South Korea. [3] \"Design and Implementation of High Speed 4x4 Vedic Multiplier\" was authored by Debasish Subudhi, Kanhu Charan Gauda, and Abinash Kumar Pala, published in Volume 4, Issue 1 1 , November 2014, with ISSN 2277 128X. [4] Jagadguru Swami Sri Bharath Krishna Tirthji\'s work, \"Vedic Mathematics or Sixteen Simple Sutras from the Vedas,\" was published by Motilal Banarasidas in Varanasi (India) in 1986. [5] Cristian Violatti provided information on \"The Vedas\" in an article titled Ancient History Encyclopedia, retrieved from https://www.ancient.eu/The_Vedas/in January 2013.

Copyright

Copyright © 2024 Swarit Pandey, Vaibhav Mohan, Kamal Bhatia, Shilpa Srivastava. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.