Design of High Speed and Area Efficient N-Bit Digital Comparator

Abstract

A digital comparator is a hardware electronic device or a combinational logic circuit. It is capable of comparing two numbers as input in binary form and determines the output. In the previous designs like in the design of XOR-XNOR(XE) with cross-coupled p-MOS, even though it occupies less area, the full swing output voltage can’t be able to produce which creates a problem when the bit width increases. To avoid this kind of disadvantages we are designing a N-bit digital comparator in a way such that it produces full swing output voltage with the improved power efficiency as well as the transistor count in the circuit also decreases. So that it can be used in several applications like scientific computations and test circuit applications etc.

Introduction

I. INTRODUCTION

A digital comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to other number. It can be used in several applications such as IR sensors, OP-amp’s, Image processing etc.

In one of the previous designs [9], an eight transistor XOR-XNOR(XE) with cross-coupled P-MOS, is used to design the comparator and it helps in improving the speed and power efficiency. But it is not applicable in the increased bit-widths because if the bit width increases it can’t be able to produce full swing output voltage.

In another design [8], it uses different logic techniques for the comparison of transistor count, power consumption and propagation delay. And to improve the propagation delay a hierarchical prefix tree structure method had been proposed [10]. However, the power consumption will be more for log2 N comparison levels for the wide input operands.  Several comparator designs have also been verified like parallel prefix tree structure’s, dynamic logics, using subtractors or multipliers in the designing process etc. each having several specifications.

In the evolving VLSI technology, it is important to design any electronic component with less area and improved power efficiency and operating speed. In this paper we are designing the comparator which is efficient in terms of speed, power consumption and area. To improve the power consumption, we have used parallel prefix tree structure method, and to produce the full swing output voltage a novel EX-OR-NOR cell had been considered from [3].

Table 1: Used symbols and abbreviations

II. DESIGN METHODOLOGY

Let’s consider 2 input operands A and B as shown in fig.1. In the comparison process, the bits will be compared form MSB to LSB. It keeps comparing until it encounters two unequal bit pairs. If the output is equal then it means that AEB. If the output is not equal then it will check for less than or greater than. In comparing the bits from MSB to LSB the bit that first encounters logic 1 is greater than the other operand. The outputs for unequal bit pairs are AGB and ALB.

III. CIRCUIT DESCRIPTION

For the proposed N-bit comparator the RTL design for a 4-bit is shown in fig.3. The circuit has been divided into two sections, they are

A. Comparison Evaluation Module (CEM)

Comparison evaluation module as the name indicates all the comparison process will be done in this section. This section has its individual steps, in each step each type of operation will be performed. In step 1, the XOR and X-NOR operations will be performed. In step 2, AND logic will be used and the inputs are the outputs of XNOR operation from step1 and equality pin(E). In step 3, NAND operation will be performed and the inputs for the NAND gate are the outputs of XOR operation in step1, E and input bits of the operand A. In step 4, the outputs of the NAND logic will be given as the inputs to another NAND gate.

Section 2 is known as Final Module. The final result will be decided in this section. The outputs of step 2 and step 4 will be provided as the inputs to the 1st NOR logic and it decides the logic o or 1 for ALB, if ALB=0 then this output and the output of step2 will be provided as the inputs for the 2nd logic and the final result will be provided.

B. Novel Ex-OR-NOR cell

This novel EX-OR-NOR cell is based on pass transistor logic and CMOS logic and this logic has been considered from [3]. It consists of 7 transistors. The M5 transistor in the cell is used for producing full swing output voltage as shown in fig6. In the feedback a PMOS transistor is connected which helps in maintain the logic level on the EX-NOR output terminal. The CMOS logic is used to improve the output for achieving the full swing on the EX-OR output terminal.

Let’s consider an example for the proposed N-bit comparator. To explain the process, we have considered a two 4-bit operands A and B, where A=1100, B=1010. Set 1 compares for the equal and unequal bit pairs. The outputs of set 1 are 1001 and 0110. The output 1001 will be the input for set 2 which includes E0=1 and the output of set 2 is AEB=0. In set 3 and 4 the NAND logic will be performed with its previous sets outputs as it’s input’s. And in set 5 the final result will be obtained i.e., ALB=0and AGB=1.

IV. AREA, POWER CONSUMPTION AND OPERATING SPEED ESTIMATIONS

Conclusion

This paper presents a novel EX-OR-NOR cell which is used in implementing the proposed N-bit comparator and also this novel cell is used for producing the full swing output voltage for larger bit-width. The estimations for power, area and the operating speed has also been discussed. With the advantages of the proposed model, it can be used in several applications such as test circuits, memory addressing logic, scientific computations etc.

References

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Copyright

Copyright © 2022 Sahithi Sunkireddy, Sahithi Thallapally, Ganesh Avula, B. Shivani Gayatri Devi. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.