Design of Power Efficient Posit Multiplier using Compressor Based Adder

Abstract

Posit number system has been used in many applications, especially the deep learning. Because of how well its non-uniform number distribution aligns with deep learning\'s data distribution, deep learning\'s training process can be sped up. The hardware multiplier is typically built with the widest mantissa bit-width available due to the flexibility of posit numbers\' bit-width. Such multiplier designs consume a lot of power since the mantissa bit-width is not necessarily the maximum value. This is especially true when the mantissa bit-width is tiny. The mantissa multiplier is still built to have the widest bit-width feasible, but it is broken into numerous smaller multipliers. At run-time, just the necessary tiny multipliers are turned on. The regime bit-width, which can be used to determine the mantissa bit-width, controls those smaller multipliers. This design technique is applied to 8-bit, 16-bit, and 32-bit posit formats.

Introduction

I. INTRODUCTION

A new datatype called Posit was created to completely supplant IEEE Standard 754 floating-point numbers. (floats). Plots do not require interval arithmetic or variable size, in contrast to previous iterations of universal number (unum) arithmetic. operands; similar to fractions, they round if a response is not precise. Larger dynamic range, better accuracy, better closure, bitwise identical results across systems, simpler hardware, and easier exception management are just a few of the compelling benefits they offer over floats. Posits never go over or under their limits, and "Not-a-Number '' (NaN) denotes an action rather than a bit sequence. An IEEE float FPU requires more hardware than a posit processing unit. Furthermore, its uneven data distribution blends well with the uneven data distribution of some uses, including deep learning. In deep learning algorithms, the 8-bit or 16-bit posit formats are frequently employed. In some scientific computation uses, the 64-bit floating-point format is replaced by the 32-bit posit format. A posit number is defined as Posit (nb,es), where nb is the overall bit width and es is the exponent bit width. Sign (s), regime (rg), exponent (exp), and mantissa are its four constituents. (frac). The bit-width of the component varies. For various values, the regime bit-width changes.

III. PROPOSED METHOD

One of the major speed enhancement techniques used in modern digital circuits is the ability to add numbers with minimal carry propagation. The basic idea is that three numbers can be reduced to 2, in a 3:2 compressor, by doing the addition while keeping the carries and the sum separate. This means that all of the columns can be added in parallel without relying on the result of the previous column, creating a two output & quot; adder & quot; with a time delay that is independent of the size of its inputs.1 bit 3:2 compressor is shown in figure 7.

Conclusion

The idea proposed in the paper is a 32-bit Posit multiplier architecture with power efficiency. Intrigued by the idea of reconstructing the multiplier unit for mantissa into smaller parts, because of the whole mantissa unit is not used entirely all the time, we have built the hardware. To limit the power consumption, we use only the necessary potion of the multiplier. Our method is evaluated for 16-bit multiplier, whereas we can extend the work for 8-bit and 32-bit posit multipliers using the same technique. For futuristic purposes, more power reduction techniques for multiplier architecture can be developed. The work need not be necessarily limited to multipliers alone. Future works can be deployed also for Posits Adder or Posits Multiply Accumulate functions.

References

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Copyright

Copyright © 2023 Mr. N. Senathipathi , R. Rasiha, R. Sadhurya, S. Sangeetha . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.