Design Wallace Tree Multiplier Using Reversible Gates

Abstract

Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS re­spectively.

Introduction

I. INTRODUCTION

Convolutional units are vital in signal proce­ssing tasks as they are heavy on computations and impact performance. The basic parts of these units are adders and multipliers, but multiplie­rs have a hefty role in se­tting the area, delay, and energy use. There is a big need for speedy, space-saving, and energy efficient multipliers in real world tasks that involve computational units [1]. Examples of these tasks are convolutional neural networks and multimedia. The act of multiplying is generally split into three parts: 1) creating partial products with an AND gate array, 2)  partial product accumulation, and 3) adding the final partial products. The part where partial products are piled up is big in setting the over all delay of the multiplier action. As a result, people who research have zoomed in on making this part better [3]. They use parallel and quick accumulation methods to make the final two terms for the  third part.

Algorithms from Dadda and Wallace  have made considerable steps in creating architecture for delay optimization in the accumulation stage. The accumulation phase delay could be further cut down by utilizing compressors over full adders and half adders [6]. The 4:2 compressor is the compressor design that is most widely used. In modern time­s, the exploration of multipliers in approximation context has risen since they are in great demand for the successful creation of area and power optimized designs. These designs are vital for applications such as multimedia processing, neural networks, and signal processing, which can handle errors. Investigations into such optimizations have been active in areas such as CMOS, FPGA, pass transistor, and FinFET based multiplier implementations [7].

This paper aim at reduction of power consumption and delay of  8x8 Wallace tree multiplier by using the reversible logic gates and wallace tree reduction technique [4]. This is accomplished by the use of simple  circuits like half adder, full adder, 4:2 compressor which are realized using the reversible logic gates like BJN gate, Peres gate and CNOT gate etc.

A. Basic Multiplication Process

The multiplication of two binary digits involves two elements they are multiplicand and the multiplier. The proce­ss consists of generating partial products. If the multiplie­r bit is '0', then the partial product will be always '0'. If the multiplier bit is '1', the partial product will be the same­ as the multiplicand bit [2]. The final step is addition of the­se partial products using the half adder and full adder circuits. The block diagram shows multiplication between M-bit multiplicand and an N-bit multiplier [5].

II. LITERATURE SURVEY

1. Using parallel prefix adders, we analyse and construct a high-speed Wallace tree multiplier for very large-scale integration circuits.

Utilising four distinct PPAs the Kogge stone adder, the Brent Kung adder, the Han Carlson adder, and the Ladner Fischer adder four distinct Wallace Tree multiplier constructions have been created [13]. In phase 2, these adders are applied in the last addition procedure to enhance the multiplier's operating performance. Both steps of the multiplier operation are identical. As a first step, AND gates are used to create partial products. Use of half and full addition algorithms in a step-by-step fashion is used in Phase 2 to combine the partial products produced in Phase 1. Using PPA, the suggested design completes the second phase's incorporation of incomplete products [19].

2. Array Multiplier with Reversible Logic Structure for High Performance

The simplest definition of a multiplier is a circuit of logic that performs multiplication by two or more distinct integers. If we're going to discuss multipliers, it will be from the perspective of the designer [12], not the viewer. The proposed array multiplier uses six full adders based on reversible multiplexers and four reversible half adders. There is a connection between the array's multiplier reduction stage and this array full adder that is structured around multiplexers. There is a hierarchical structure to the partial goods in the array. At each level, there are three bits, therefore a complete adder is needed. Follow up with the previous explanation to understand how this complete adder works. There is a difference in operation when using the second multiplexer of a complete adder [16]. Below, carry bits are used as inputs to the second multiplexer. Reducing power consumption and chip space, this design increases logic circuit efficiency.

3. Logic gates with reversible inputs and their uses

Reversible logic systems are becoming more popular because of their low power consumption. Reversible logic plays an essential role in the design of low-power circuits. The significant Reversible logic synthesis may be achieved using a variety of gates, including Toffoli Gate, Feynman Gates, Fredkin Gate, New Gate Sayem, Peres Gate, and many more [8]. Here we showcase an easy-to-understand reversible gate that can be used to build more intricate circuits that can be integrated into various sequential circuits, ALUs, or, and specific circuit combinations. It gives you the rundown on the fundamentals of building. Adder circuits make use of basic reversible gates, including the Peres gate, in addition to the TSG gate [18].

III. EXISTING SYSTEMS

1) Building a Modular Architecture for Low-Power Wallace Tree Multipliers

A CBMW multiplier that is both scalable and powers down quickly is suggested. Because of this, the Wallace tree multiplier may be efficiently and easily implemented on FPGA and ASIC computers [9]. Superior to previous 7:3 counter designs, the multiplier under consideration makes use of a multiplexing and XOR gate dependent adders. The product is then generated by adding the output from the previous stage with the carry form the previous column using a single fast adder in the final step.

One 7:3 counters is used each stage, which reduces hardware requirements and significantly reduces power consumption owing to enhanced localization [17].

IX. ACKNOWLEDGMENT

We are very grateful to Mr. G. Shyam Kishore, Assistant Professor in the ECE Department of CMR College of Engineering and Technology for his valuable suggestions and help throughout our project  and paper work completion.

Conclusion

The design of a Wallace tree multiplier that makes use of a reversible compressor, a full adder, and a half adder is shown in this work. This research demonstrates that the power consumption performance generated by the Wallace tree multiplier may be improved by using reversible gates. The Verilog programming language is used to implement the Wallace tree multiplier architecture. The Xilinx ISE design suite 13.2 used for simulations and synthesises results.

References

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Copyright

Copyright © 2024 Mr. G. Shyam Kishore, S. Jaya Prakash, B. Sachin, D. Puneeth. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.