Energy-Efficient Approximate Multiplier with Flexible Precision

Abstract

The method that can be utilized to increase accuracy and decrease energy use is approximate multiplication. A key component of many error-tolerant applications is multiplication. Approximate multipliers are increasingly utilized in energy-efficient computing for applications tolerant of inaccuracy. Apart from multiplier performance, determining the appropriate approximate multiplier is challenging due to considerations of area and delay. Therefore, selecting the type of approximate full adder (FA) becomes a crucial decision-making factor. These adders are employed for summing partial products in multipliers. This study presents the design and evaluation of an approximate multiplier employing four distinct approximate adders. The design undergoes simulation and synthesis using Xilinx and Model Sim. Compared to previously proposed approximate multipliers, the proposed circuits demonstrate substantial reductions in area, time delay, and power consumption. According to experimental data, the area, latency, and average power consumption of the suggested adjustable approximate multiplier can be lowered by 10%, 34.96 ns, and 300 mW when contrasted to the Wallace tree multiplier.

Introduction

I.  INTRODUCTION.

Multipliers play a vital role in various applications like digital signal processing (DSP), computer vision, multimedia processing, image recognition, and artificial intelligence. These applications often require numerous multiplications, leading to significant power usage, especially challenging for mobile devices. Many studies propose reducing power consumption in multiplier circuits to address this issue. One approach is to approximate multiplication, especially for applications where some level of error tolerance is acceptable, such as those related to human perception. Because human senses have limitations, precise computation results may not always be necessary. The approximation multipliers reduce cell space, time delay, and power consumption at the expense of precision [1].

The prevalence of modern computing systems, whether they are pervasive, portable, embedded, or mobile, has sparked a rising need for ultra-low power consumption, compact size, and superior performance. A developing paradigm called approximate computing provides a way to accomplish these goals while compromising arithmetic precision. Many domains, including multimedia and big data analysis, can tolerate a certain level of computational inaccuracies, making them prime candidates for employing approximate computing techniques. focuses primarily on the design of approximate arithmetic units in hardware, including adders and multipliers, at various abstraction levels, including transistor, gate, RTL (Register Transfer Level), and application [2].

An approximate multiplier in VLSI design usually has 3 stages.

1. Partial-product generation-input operands are decomposed into smaller sub-multiplications, which are combined to form the full product.
2. Accumulation-The input operands are combined to form the full product.
3. Final The output is produced depending upon the input operands.

The majority of approximation multipliers shorten the carry chains with configurable errors. When the operand's bit width rises, the algorithms utilized in the designs produce bigger magnitude errors for smaller numbers.

Power area and delay efficiency of approximate multiplier design-Removal partial product generation and accumulation for lower order input operands.

The computational method can therefore be applied to situations where an approximate answer is adequate for the intended purpose, but it also delivers a potentially incorrect result instead of a guaranteed one.

II. METHODS FOR DIGITAL ARITHMETIC [RELATED WORK]

In practically all applications involving digital signal processing, multiplication is a fundamental arithmetic operation. Hardware multipliers are necessary for DSP systems to effectively implement DSP algorithms. The digital processing units' speed is directly impacted by the multiplier's “speed [3–5].

The literature has a large number of fast multipliers that can be utilized to” create an effective digital oscillator [6,7-10]. The addition is the fundamental function of a multiplication algorithm, regardless of the multiplicity technique. We examine the most typical adder architectures in this section. Multi-operand addition methods are utilized to better improve multiplication addition “processes [11].

A. Carry Save Adder (3:2 Adder/3:2 Counter)

The Carry Save Adder (CSA) belongs to the category of redundant number system adders. It is employed for adding multiple binary vectors, such as x, y, and z, to produce 2 binary vectors—S and C—where x + y + z = S + C. This addition operation can be executed in constant time (O(1)) as the carry bits are preserved in the C vector, eliminating the need for carry propagation. The final binary vectors (S + C) are added using a conventional number system adder, such as the carry look-ahead adder, to yield the result of the multi-operand addition. The FA can be viewed as a 1-bit CSA, as” Fig. 2 illustrates.

Conclusion

In this investigation, several approximation multipliers based on approximation in partial product summation were constructed, assessed, and compared. The architecture may multiply 32-bit input and produce 64-bit output; the design space of approximate multipliers is discovered to be mostly reliant on the type of approximation FA utilized. Compared with the different existing multipliers our proposed multiplier has less area that is several Slice LUT (Look Up Table)- The area is 19200 and utilization is only 10% the minimum is the utilization is the area consumption will be less, time delay is less and power consumption is less which is 34.96 ns, and 300 mW in contrast to the Wallace tree multiplier, Booth multiplier and other existing multiplier which shows that our suggested approximate multiplier is more efficient and flexible.

References

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Copyright © 2024 Ayushi Vinodia. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.