Flipped Voltage Follower based LDOs for Precise Clocking Circuits: A Comparative Study

Abstract

This work presents a comparative study between basic Flipped Voltage Follower (FVF), Cascoded FVF (CAFVF) and Buffered FVF (BFVF) Low Dropout Regulators (LDO) along with simulation results in tsmcN40 PDK.The designs support a load current of 5u-10mA with a on-chip capacitive load of 100fF, for a dropout of 700 mV (From 1.8V to 1.1V). This work also employs both miller conmpensation and non-dominant pole cancellation techniques in BFVF to get better phase margin and PSRR. Line regulation of 3.3 mV/V and load regulation of 20.4 uV/mA was obtained for 10mA load current, with less than 0.5 uS response time in BFVF.

Introduction

I. INTRODUCTION

The motivation for developing Low Noise LDO for clocking circuits stems from the critical need for precise and stable timing signals in electronic systems. Clocks are fundamental in synchronizing various components within a circuit, and any noise or instability in the power supply can directly affect the performance of these clock signals. Noise in the power supply can introduce jitter and phase noise into the clock signal, which can degrade the overall performance of the system, leading to errors and reduced reliability.

Low noise LDOs are specifically designed to minimize power supply-induced variations, providing a clean and stable voltage to clock circuits. This ensures that the clock signals remain accurate and consistent, which is essential for high- performance computing, telecommunications, and data pro- cessing applications. FVF based LDOs have less reponse time compared to traditional LDOs and good noise performance. Another advantage is that it doesn’t require large load capac- itor and can work sufficiently well with as low capacitance as 40pF.

II. LITERATURE SURVEY

Literature review on different LDO architectures is made first and then FVF is choosen as it has fast transient response, minimum load and line regulation, appreciable PSRR and very low RMS noise. In [1], the methods for slow loop feedback in FVF are described and tri-loop architecture is implemented, PSRR max of -10dB is achieved. This also uses a Super Source Follower (SSF) , a load cap of 300pF is used and UGB of 400 MHz is achieved. Paper [5] explains in detail all the FVF architectures available and their advantage and disadvantage. It also discusses the design aspects of the CAFVF and BFVF, along with stability and bandwidth expansion methods. In [9] , overshoot and undershoot damper along with Negative Capacitive Circuit (NCC) are used to achieve -76 dB PSRR at 1 MHz and 131 mV/V line regulation. In [14], tri-loop architecture is implemented with SSF based LSFVF, which achieved 600MHz UGB, line regulation of 37.1 mV/V and load regulation of 1.1 mV/mA. It had voltage variation of 82 mV at Tedge.

In [6], difference between on-chip and off-chip topologies in LDO architectures are explained and design considerations for on-chip capacitor architectures are elucidated. Also enhance- ment of stability and PSRR using multiple error amplifiers and frequency compensation stage are mentioned with brief introduction to different topologies like differentiator, trans- impedance and voltage subtractor.

In [15], the methods of increasing bandwidth of FVF loop are discussed. The effect of introducing Source Follower, Super Source Follower and Voltage Combiner are explained and results are shown. In [8], N-type FVF is implemented with SSF and cascoded current sources and PSRR of -84dB is achieved at 1 MHz. It also has very less noise of 17.2 nV/sqrt(Hz) is obtained by using low load capacitance of 50 pF.

Conclusion

The conclusion drawn from three designs are elucidated in Table TABLE I COMPARATIVE ANALYSIS Para- meters Architectures FVF CAFVF BFVF Min current High Zero Zero Poles Two Three Four Dom. pole node VG VG VH Line regulation Not settling More Less Load regulation High Low Low Vspike Low High Low PSRR Worst Moderate Good UGB High Moderate Moderate Loop gain Low Moderate High The target output voltage was 1.1V with 3% variation, that means output can vary from 1.067 to 1.133V. The actual output varied between 1.107 to 1.114V across all corners, which is well within the target. DC Load regulation is 20.4uV/mA. DC line regulation is much less than 1mV/V and transient line regulation is 3.33mV/V. PSRR of -9.3 dB maximum was observed and overshoot and undershoot were in control, both being less than 2.5mV. The future scope of the project can be listed as below : 1) Different approach to be taken for frequency compensation, as miller capacitance will worsen the PSRR 2) PSRR has to be reduced still, by applying different methods and techniques 3) Techniques to decrease the load capacitor further has to be studied and implemented 4) Layout to be implemented and verify post-layout simulation results 5) The design has to be tested with a real load inside the chip, rather than simulations

References

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Copyright

Copyright © 2024 Chinmay D Hegde, Vishnu Sai Jayam, Prakash Chand Kuve, Dr. Srividya P. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.