Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Abstract

In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

Introduction

I. INRODUCTION

Vedic mathematics was more briefly researched by Bharati Krishna, who was a research scholar, specified that overall 16 sutras and 13 sub-sutras describes Vedic mathematics which in turn increases the simplicity of solving mathematical equation for computation.

. For these task multiplications is a fundamental hardware part. Hence, the presentation of the multiplier is a key component in deciding the exhibition of the whole framework. This is on the grounds that, the multiplier is the slowest and most tedious component in the framework. Along these lines, the enhancement of the multiplier speed and area is a noteworthy test for the framework architects. This test can be effectively overwhelmed by the utilization of old Vedic mathematics techniques.

Binary multipliers are used in digital circuit plan which makes them quick, dependable and effective to execute any task. Contingent upon the course of action of the segments, there are various kinds of multipliers accessible. Vedic multiplier is based on Vedic mathematics containing 16 different sutras which are divided based upon its execution of different arithmetic operations. The intensity of Vedic mathematics isn't just kept to its effortlessness, consistency, yet in addition it is sensible. Its high level of importance is ascribed to the previously mentioned certainties. The logic behind Urdhva Tiryakbhyam sutra is especially like the conventional array multiplier.

Nikhilam Sutra is all from nine and last from ten. To perform the multiplication operation, it finds out the compliment of the large number from its nearest base. Ekanyunena Purvena implies one not exactly past one or one short of what one preceding. This sutra is implicable for multiplication of numbers where multiplier is 9 or cluster of 9. Squaring task is helpful in digital signal processing (DSP) applications in which multiplication activity requires repetitive addition operations. Ekadhikena Purvena Sutra is summed up for finding square of a number.

A multiplier usually has three steps. The first step is the partial product generation (PPG) process. For example, AND gates can be used to generate a partial product matrix (PPM) for an unsigned multiplication.

The second step is the partial product reduction (PPR) process. By using the Dadda tree approach or the Wallace tree approach, the PPM can be reduced to become two rows. The third step is the final addition. An adder (called the final adder) is used to perform the summation of the final two rows. For an N-bit multiplier, a (2N-1)-bit adder is required for the final addition.

Various adder architectures have been proposed for the trade-offs among delay, area, and power. Furthermore, various MAC unit models can be developed by replacing the multiplier as well as the accumulator (adder) with various architectures. Comparisons on delay, area and power among different MAC unit models are reported.

The most vital task in mathematical operations is the multiplication which can be executed through many ways such as MAC, CIAF (Computations Intensive Arithmetic Functions) and are presently applied in DSP applications. As the multiplication is the most important task, speed of any system is decided upon the type of multiplier used for the operation. This work presents different multiplier architectures which are fast and low power based on Vedic Mathematics. Depending upon the arrangement of the components, there are different types of multipliers available.

Jain and A. Jain compared two different architectures such as Array and Vedic to know the best architecture for multiplication in turns of power and delay characteristics. Studying and analyzing power and delay characteristics, author came to know that “Urdhva Tiryakbhyam” multiplier is the best multiplier compared to array and Nikhilam multiplier when compared to delay and power calculations.

II. EXISTING SYSTEM

The existing system presents 32-bit RISC Processor using Vedic Multiplier.The function of the processor is to execute each and every instruction set efficiently as per the machine language. In Processor, ALU inputs consist of instruction (machine word) which is operation code (opcode) and some operands. So the opcode tells the ALU which and what operation is to be performed then these operands are used in the operation.

There is a small set of data holding place that is known as Register bank. The ALU stores the result of operation in accumulator which later on is placed in a storage register and it checks the bits and indicates whether the operation was performed successfully. If not successfully executed then some type of status will be shown i.e. even known as Z-Flag or status register. Its function is to execute programs and operate efficiently for the data stored in memory. A processor has a set of instructions which is nothing but a command to perform a task in a computer. The control unit holds the instruction to be executed. In CPU, the registers such as address register, data register and an instruction register is present. The performance of the CPU is to fetch, decode and execute the operations on memory according to the registers. The task of IR includes the decoding the op-code, determining the instruction, determining which operands are in memory, retrieving the operands in memory then assigning a command to a processor to execute the instruction. This is done with the help of control unit which generates the timing signals that controls the various processing elements which involves in execution of the instruction.

The MAR is also called as address buffer; the address in the program counter is applied to memory so after the increment in PC to the next address the current instruction is stored in the Memory location. The MAR is completely loaded with Binary words which point the location of the word in RAM. This location stores the instruction in it.

Ankita Yadav et al. [1] in this paper presents a 16-bit RISC processor designed using Verilog Hardware Description Language (HDL) and simulated in the Xilinx ISE 14.7 design suite. The main achievement is the implementation of the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) using Vedic Sutras. The proposed RISC processor is simple and capable of executing 14 instructions. The design achieves 44% savings in power and 12% reduction in delay compared to conventional ALU and MAC. When integrated with other blocks, the 16-bit Vedic processor reduces delay by 34% and saves around 88% power compared to a conventional processor. The key features of the designed RISC processor include improved speed, reduced power utilization, and less area utilization. The Vedic processor is implemented using Xilinx ISE 14.7 Design Suite in Verilog and verified using QuestaSim of Mentor Graphics.

Aditi Chhabra et al.  [2] in this paper presents an alternative approach to designing the MAC unit of a neural network using an 8x8 Vedic Multiplier. The network consists of four 4x4 Vedic Multipliers and a 16-bit Rippler Carry Adder instead of a conventional array multiplier. The paper compares different configurations of Vedic multipliers and traditional array multipliers, aiming to obtain an alternative approach for the realization of the MAC unit of the neural network. The proposed network achieves an accuracy of 88%, which can be increased by increasing the precision of the multiplier. The paper also highlights the emerging Reversible Logic Technology in Vedic Multipliers. The proposed network prioritizes power efficiency and maintains the precision of the multiplier, resulting in an accuracy of 88%.

Aslesa Singh, et al. [3] presented in this paper about a 32-bit Datapath with RISC-V instruction set architecture based on RV32I CPU instruction set. The processor is optimized using a six staged folded pipeline core and tested on two Virtex family FPGA boards. The Ultrascale board offers better power-performance tradeoff at higher costs, with a higher total chip power but lower dynamic power. The design is parameterized and user-defined, with over a dozen options for power efficiency or performance. The RISC-V environment allows for extensive tweaking, making it suitable for error-free placement on devices. The design can be widely used in upcoming processor designs with a RISC-V ISA due to its unique design pipelining component and highly parametrized core.

Tariquzzaman, et al. [4] presented in this paper about a 64-bit RISC processor with a Vedic multiplier feature (using the Nikhlam Sutra), implemented using VHDL. The processor is designed to reduce execution time and address large memory up to 16 Exabytes. The Vedic multiplier architecture is 135.05% faster than conventional multipliers, reducing time in multiplication operations. The design is verified on the Xilinx ISE 10.1i simulator and programmed using VHDL. Future work will focus on increasing instructions and creating a pipelined design with less clock cycles per instruction.

Shradda Lad et al. [5] presented in this paper about a highly efficient Vedic multiplier unit using various Sutras of Vedic Mathematics. The design, synthesis, and simulation of a 16-bit Vedic multiplier unit were performed using Vivado 17.1 and Verilog. Performance parameters like delay, power, and area were analyzed. The Ekadhikena Purvena sutra achieved a 70.26% reduction in area and a 90.41% increase in speed compared to Urdhva Tiryakbhyam. The Nikhilam sutra provided the optimum area and delay, with the most effective in terms of power. These performance values can be used for selecting multipliers in image and signal processing applications and digital filters.

Rashmi Samanth, et al. [6] presented in this paper about the design and implementation of a 32-bit Functional unit for RISC-based processors, including Arithmetic and Logic Unit (ALU) modules. The design uses multiplexers for operations and is compared to conventional Microprocessor without interlocked Pipeline Stages (MIPS). The design reduces power dissipation by 30.449%, area by 6%, and delay by 34.49%. The design uses behavioral and structural modeling, and simulation is supported using Xilinx ISE and Cadence RTL Compiler.

III. PROPOSED SYSTEM

The function of the processor is to execute each and every instruction set efficiently as per the machine language. ALU is the combinational circuit which means Arithmetic and Logical Unit. This unit is designed to perform various numbers using various instruction sets. In Processor, ALU inputs consist of instruction (machine word) which is operation code (opcode) and some operands. So the opcode tells the ALU which and what operation is to be performed then these operands are used in the operation.

There is a small set of data holding place that is known as Register bank. The ALU stores the result of operation in accumulator which later on is placed in a storage register and it checks the bits and indicates whether the operation was performed successfully. If not successfully executed then some type of status will be shown i.e. even known as Z-Flag or status register. Its function is to execute programs and operate efficiently for the data stored in memory. A processor has a set of instructions which is nothing but a command to perform a task in a computer. The control unit holds the instruction to be executed. In CPU, the registers such as address register, data register and an instruction register is present. The performance of the CPU is to fetch, decode and execute the operations on memory according to the registers. The task of IR includes the decoding the op-code, determining the instruction, determining which operands are in memory, retrieving the operands in memory then assigning a command to a processor to execute the instruction. This is done with the help of control unit which generates the timing signals that controls the various processing elements which involves in execution of the instruction.

The MAR is also called as address buffer; the address in the program counter is applied to memory so after the increment in PC to the next address the current instruction is stored in the Memory location. The MAR is completely loaded with Binary words which point the location of the word in RAM. This location stores the instruction in it.

“Urdhva Tiryakbhyam” (Vertical and Crosswise) sutra (Algorithm). It is a general multiplication formula equally applicable to all cases of multiplication. The algorithm generates all partial product and sum in one step. The algorithm is generalized for nxn bit number .This Multiplier has advantage that when we increase the number of bits ,gate delay and area increases very slowly compared to other multipliers. Due to its regular structure, Multiplier processing power increase by increasing the input and output data bus widths. The digits on the two ends of the line are multiplied and the result is added with the previous carry. When there are more lines in one step, all the results are added to the previous carry. The least significant digit of the number thus obtained acts as one of the result digits and the rest act as the carry for the next step. Initially the carry is taken to be as zero.

Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and single output line. One of these data inputs will be connected to the output based on the values of selection lines. Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each combination will select only one data input. Multiplexer is also called as Mux. 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The block diagram of 4x1 Multiplexer is shown in the following figure. In this modified full adder consists of two 4:1 multiplexers here a, b are two selection lines for both the multiplexers C is the only input to the multiplexer that gives sum as output, 0,c,1 are the inputs for the multiplexer that gives carry as the output. After studying the conventional full adder design, a multiplexer based design is modeled by identifying its operation using truth table and the input and output values when logic 0 and logic 1 as input at the consequent input line. Using this multiplexer based adder designs it can be observed that there is a maximum reduction in the gate count of the logic design, thus making it an efficient implementation.

Conclusion

In this paper, 64- bit RISC processor based on Vedic sutra –Urdhva Triyakbhyam in ALU has been implemented. Vedic Multipliers are used for multiplication to improve the speed and reduce the area and power budget of the multipliers and in addition to it adders are getting replaced with mux-based adders which will improve the area efficiency slightly and hardware complexity will be optimized compared conventional adders. The utilization of Vedic Multiplier allows for a high speed, low power and reduction in the overall gate count, contributing to a more streamlined and resource-efficient architecture. For the 64 bit we are unable to optimize with divide and conquer based adder implementation so we can proceed with MFA implementation along with programmable clock for extending it to applications. In this work, Vedic processor is designed using Vedic MAC and Vedic ALU along with other conventional blocks in processor. The comparison of simulation result of Vedic ALU and MAC design is done with the existing ALU and MAC results by using mux based adders not only for multipliers addition operation in ALU can also be improvised. The 64-bit Vedic processor reduces the Area, delay compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

References

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Copyright

Copyright © 2024 Thulasi Venkata Sai, Sunku Vinay, Reddyvari Tharun, Vidyalavaru Subhash Reddy, Sadhu Vinay Kumar, G. Padma Priya. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.