Low Drop-Out Regulator

Abstract

The Low Dropout Regulator (LDO) is a kind of linear voltage regulator that uses transistors as variable impedance components to regulate the voltage and current. Due to its low noise and quick transient response, it is often deployed in portable equipment. We will develop, simulate, and analyse a low-dropout regulator in this project. The regulator is based on the traditional seven-pack approach, which reduces the number of components, simplifies the design, and also reduces power consumption. The system is developed and simulated in the cadence virtuoso environment at the 90 nm cmos scale of technology. It describes a three to five volt, 100 millivolt low dropout regulator. The experimental findings demonstrate that a minimal voltage drop may be achieved by combining a two-stage operational amplifier with a bandgap voltage reference, as well as a feedback element and a pass device.

Introduction

I. INTRODUCTION

Low dropout voltage regulator is basic building block of portable handheld electronic devices as well as automotive industry. The constant output voltage is generated by regulator by using a reference voltage. Reference voltage should be independent of process, voltage, and temperature variation. Increasing demand of portable handheld battery-operated devices forced the sub circuit to operate in low voltage high current efficiency condition for better battery lifetime. Battery life is determined by quiescent current. As VLSI technology is getting mature integrated power management for SOC is required. Miniaturized and fully on chip regulator voltage regulator should be stable for a wide range of load variation and have high PSRR over a wide frequency range. Basics of low drop out regulator, its market demand and motivation for the design is discussed in this paper. The design is defined to meet future regulator demand. A series low-dropout regulator (LDO) ensures a stable DC voltage [1], even when dealing with a low dropout voltage [2]. The dropout voltage refers to the difference between the input and output voltages at which the regulator ceases to effectively regulate. In this proposed work, a MOS transistor is positioned in series between the input and output, acting as a variable resistor to control the output voltage [3]. The feedback regulator monitors the output voltage and compares it with a reference voltage. Any difference detected generates an error signal in the comparator, which adjusts the impedance of the pass transistor, thereby regulating the output voltage.

For proper operation, the input voltage to the regulator must exceed the output voltage by at least the dropout voltage to remain within the regulation range. Additionally, the output impedance should be kept low [5] for optimal performance.

LDOs can be categorized based on various parameters, such as high power or low power, high dropout or low dropout, and output pole dominant or capless. Low-power LDOs typically offer maximum output currents in the range of mA, making them suitable for use in portable handheld electronic devices [4]. The different design options for LDO are mentioned below:

A. Voltage buffered LDO

After the error amplifier, a voltage buffer drives the gate capacitance of the pass element, increasing slew rate and providing excellent transient responsiveness.

B. LDO with Feedback Current Amplifier

The current amplifier is used in this LDO. The output current is sensed by the current amplifier, which generates extra current and raises the slew rate at the gate of the pass element.

C. LDO with Miller Capacitance

Miller capacitance is used in this design. We may enhance phase margin and hence stability by changing an exact capacitance value.

Conclusion

In the paper, initially, a brief introduction about Linear Low Drop-Out Voltage Regulator (LDO) is given along with why it is required, different topologies of linear voltage regulators, and their design considerations. After that, a brief overview of the voltage bandgap reference is given. It is observed that all nanometre linear voltage regulator design topologies are stable only for a certain output capacitor range. So, there is a great challenge to drive load blocks with different input parasitic capacitance. Any capacitor sub-unity gain positive feedback linear voltage regulator is the most efficient, effective, and stable design topology in nanometre design technology. It is observed that any capacitor sub-unity positive feedback linear voltage regulator is stable for any value of output capacitor, has a wide range of input voltage variation, small peak-to-peak output voltage variation, small chip area for the same load driving capability and output voltage. Although having all these advantages in any capacitor sub-unity gain LVR, it is observed that for the same load current, quiescent current increases, which is because of scaling down of process technology. It adversely affects the battery lifetime of portable electronic devices. But it is acceptable as both design and silicon are getting mature. Due to a small capacitor at the output and positive feedback, settling time increases. At high frequency, Power Supply Rejection Ratio (PSRR) drops, i.e., at high frequency, more noise appears at the output. Overall, the design technique has comparable performance without any restriction on the output capacitor value. To overcome all these challenges, work is ongoing on new design topologies that provide better PSRR even at higher frequencies.

References

[1] S. Franco, “Design with Operational Amplifier and Analog Integrated Circuits”, New York: McGraw-Hill Publishing company 1988. [2] M. Mirovic, “Integrated Circuits: A User’s Handbook”, Reston, Virginia: Reston Publishing Company Inc 1977. [3] P. R. Gray and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits”, New York: John Willey & Sons Inc 1993. [4] F. Goodenough, “Low Dropout Linear Regulator”, Electronic Design, PP 65-77 May 13, 1996. [5] J H Mohammed Ismail, “CMOS High Efficiency on chip power management”, Springer Publication. [6] Dr. Qadeer Ahmed Khan, “Power Management Integrated Circuits”, NPTEL. [7] R. J. Milliken, J. Silva-Martínez and E. Sánchez-Sinencio, “Full On-Chip CMOS low-dropout voltage regulator,” IEEE Trans. Circuits SystI, Reg. Papers, vol. 54 PP. 1879-1890, Sep. 2007. [8] “Power Management Technique for Integrated Circuit Design”, STMicroelectronics.

Copyright

Copyright © 2024 Jagadish Shrishail Kalaghatagi, Sphoorti K. Kurandwad, Nikhita Jagadeesh Battur, Vyas R Murnal. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.