Performance Analysis of Deep Sub Micron Two Quadrant Analog Divider Circuits

Abstract

Current mode Analog Dividers are widely used in various circuits such as fuzzy logic controllers, neural networks, adaptive filters and variable gain amplifiers. When these current analog divider circuits implemented in DSM technology, many of the second order effects starts deteriorating its performance. Most of the available literatures on analog dividers are reporting performance of these circuits implemented using long channel MOSFETs. Hence it is a peak time to compare the performance variation between various proposed analog circuits implemented in lower technological nodes. This is for identifying most reliable circuit which safely works in this node. .In this work a comparative performance analysis of two quadrant CMOS analog divider against two quadrant CMOS approximation divider using 45nm technological node has been carried out. The obtained result indicates that Approximation Divider is reliabie than two quadrant CMOS analog divider. The entire work is carried out using Tanner software.

Introduction

I. INTRODUCTION

Analog signal processing find applications in portable equipments, wireless nano sensors or medical implantation devices because of their compact implemented structure due to low power  consumption and speed [2].  Analog Dividers are widely used in current mode analog circuits such as fuzzy logic controllers , neural networks, adaptive filters and variable  gain amplifiers [3].  Most of the available analog divider circuits implemented using long channel MOSFETs [4-6].  When current  divider circuits uses DSM technology ,many of the second order effects deteriorating performance.  The reduction of the channel length of the transistor is the most common features of the modern CMOS technology. With the introduction of DSM CMOS technologies (minimal channel length below 100nm) designers of analog circuits are facing new challenges at different stages of the design [1]. The common second order effects are body effect, channel length modulation and subthreshold conduction [7]. This work aim to fill that literature gap. In this work a comparative analysis of two quadrant CMOS analog divider [4] against two quadrant CMOS approximation divider [6] has been carried out. This is  for identifying  most reliable circuit which safely works in DSM node. This work aim to explore the functionality and performance variations of settling time and resolution.

Section II compares basic working difference of two  analog divider circuits such as two quadrant CMOS analog divider against two quadrant CMOS approximation divider  and it  also gives an overview of various second order effects arises in DSM circuits.. ,  Statement of problem and solution methodology are discussed in section III. Section IV consolidates the various results obtained and the conclusion remarks and future scope of this work is narrated in  Section V.

II. REVIEW OF LITERATURE

This work mainly focuses on two types of analog dividers. The first circuit under study is a two quadrant CMOS analog divider, where , the numerator and denominator input data are provided to the circuit as equivalent currents  where as the output quotient is a voltage. In this circuit which some transistors operate in the triode region. The second structure two quadrant CMOS approximation divider  the numerator and denominator data are currents and output also derived in current This circuit developed by using two variable second-order Taylor series approximation.  The main three second order effects which play prominent role in DSM circuits are body happens if  the bulk effect, channel length modulation and subthreshold conduction.  Body effect voltage of an NFET drops  below the source voltage  ie Vb<0  more holes attracted to the substrate connection leaving a large negative charge behind. It results in the widening of  depletion region.

As a function of that threshold voltage increases.   As in the case of channel-length modulation , actual length of the inverted channel gradually decreases as the potential difference between the gate and drain increases.  This is the channel-length modulation.  Even for gate source voltage less than threshold voltage the drain current is finite, but it exhibits an exponential dependence on gate source voltage called subthreshold voltage.

III. PROBLEM STATEMENT AND SYSTEM METHODOLGY

Most of the literatures on analog dividers are discussing there performance when they are implemented in long channel MOSFETs. Hence there is lack of information about the performance and reliability  of these circuits when they are implemented using lower technological node such as 45nm.  This work aim to fill that literature gap. A comparative performance analysis of two prominent analog divider circuits are carried out in work.The aim of this work is to simulate and study the comparative performance variation of  two quadrant Analog dividers in 45nm technological node.    Spice tool from TANNER is used for this purpose.

Conclusion

Parameter Analog divider-1 Analog divider-2 Settling time 2.85uS 3.85uS Resolution 0.2mV .02mV Relative error more less In this paper , the performance of two analog dividers namely CMOS analog divider and approximation divider are compared according to settling time, resolution and relative error and it is verified that the Analog divider is more reliable than Approximation divider. In this paper process variability is not considered so proposing Monte carlo analysis for reducing the process variations.

References

[1] Overview and comparison of methodologies for design of deep submicron cmos processes, aleksandar p radev, ieee xplore 08-sep-2022 [2] Synthesis of computational structures for analog signal processing , cosmin radu popa, spinger sciences+business media [3] Cmos current-mode companding multiplier/divider and its nth-root kuo-jen lin,chih-jen cheng andjwu-e chen, department of microelectronics engineering chung hua universitytaiwan 300 [4] Two quadrantcmos analog divider c.dualibe, mverleysen and p jespers electronic letters 11th june 1998 vol.34 no.12 [5] Liu,w, s.i liu and s.k wei cmos current mode divider and its applications,”ieee trans.circuit systems ii, express briefs,52,(3), pp 145-148,2005 [6] Two-quadrant cmos approximation divider , kuo-jen lin department of microelectronics engineering chung hua university taiwan 300 [7] B.Razavi, design of analog cmos integrated circuits. mcgraw hill, 2000

Copyright

Copyright © 2023 Minikumari G. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.