Multi-Level Inverter (MLI) has gained significant significance in medium power and medium voltage AC drive applications. Various topologies have been developed in the design of MLIs. Hybrid topologies are emerging to minimize component requirements and reduce switching losses. This paper introduces a comprehensive analysis and functioning of the asymmetrical seven level multi-level inverter topology. The modeling process is executed using the MATLAB Simulink environment.
Introduction
I. INTRODUCTION
Due to their drawbacks such as the need for more switching elements, additional switching losses, bulky driver circuit requirements and high dv/dt problems, conventional two-level inverters are becoming outdated in industrial drive applications[1]. To address these challenges, multi-level inverters have emerged with different topologies. The traditional topologies include diode clamped, flying capacitor, and cascaded H-bridge configurations [2-5].
Among these, diode clamped and cascaded H-bridge topologies have gained prominence in various applications [6-8]. The diode clamped topology requires only one DC source, enabling different voltage levels by connecting capacitors in series. However, this approach presents a voltage balancing problem. In contrast, the cascaded topology requires several DC sources, reducing design complexity [9-10]. The flying capacitortopology faces drawbacks related to voltage balancing and control circuit complexity. Consequently, researchers have explored various combinations of these basic topologies, leading to the emergence of cascaded H-Bridge topologies as a potential solution [11-14].
The symmetrical seven level multi-level inverter requires three voltage sources of equal magnitude and 12 switching devices per phase. In case of asymmetrical seven level MLI requires only two voltage sources of different values and requires 8 switches. Hence the efficiency of asymmetrical MLI is more than symmetrical MLI.
II. STRUCTURE OF ASYMMETRICAL SEVEN LEVEL CASCADED MLI
Asymmetrical topologies are the latest structures, where the cascaded series inverters have distinct internal dc voltage sources, uses less switching devices. The significant feature of the proposed multilevel inverter topology is the reduction of switches and consequently minimizing the switching losses.
The three phase circuit structure is represented in the figure 1. The circuit in figure 2 is the standard single phase asymmetrical seven level MLI representation. The neutral point is taken from the bottom inverter. There are seven switch combinations to produce seven-level voltages across the load.
References
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