Studying the Performance of Underlap GAA-FET

Abstract

This paper investigates the performance of underlap Gate-All-Around Field Effect Transistor (GAA FET) of 22nm gate length and evaluates the short channel performance of the device. Underlap GAA FET structure can be utilized to increase the drive current of the nanowire devices. In this work, underlap rectangular GAA FET is designed by extension of underlap regions on source/drain of GAA FET to increase the performance. This underlap device is increasing the capacitances by adding the fringing capacitances to parasitic capacitances which increases the fringing field from gate electrode to underlap regions. In this also investigating the electrical parameters on various performance metrics like threshold voltage (Vth), ON current (ION), OFF current or subthreshold leakage current (IOFF), ON-OFF current ratio (ION/IOFF) and short channel effects such as Subthreshold slope (SS) and DIBL (Drain Induced Barrier Lowering) of underlap GAA FET are systematically evaluated and analysed. In the present study, GAA FET and underlap GAA FET device performances are investigated through ATLAS device simulator from Silvaco.

Introduction

I. INTRODUCTION

To achieve high operational speed, low cost, and better performance of conventional transistors, the dimensions need to be downscaled to the sub-nanoscale region. The concept on device scaling law [1, 2] and advancements of CMOS technology, physical scaling of MOSFETs has been continuously shrinking in accordance with the standard of ITRS [3]. The issue of the nano-scale regime has led to continuous downscaling of MOSFET devices. Due to aggressive downscaling, reaches its limit facing short-channel effects (SCEs) occur in case of conventional single gate MOSFETs [4], which can observe because of the dominance of the junction of a minimal of channel in the time of escaping gate control [5]. The reduction of metal-oxide-semiconductor field effect transistor (MOSFET) dimensions will degrade the gate control over the channel due to close proximity between source and drain. This leads to increase various short channel effects (SCEs) such as hot carrier effect, threshold voltage roll-off, and substrate bias effect [1, 2]. Many new devices have been introduced beyond Moore’s era [3–5] to suppress the SCEs and enable further scaling down of the device. Similarly, a number of multi-gate silicon on insulator (SOI) technologies have also been proposed to replace the conventional MOSFET [6, 7]. FINFET is the industry-standard complementary metal oxide semiconductor technology for sub-22 nm node very-large-scale integrated circuits. Due to multiple gates controlling the thin, fully depleted channel, FinFET shows improved short-channel performance compared to the single-gate planar MOSFET. To maintain acceptable short channel performance in FinFET, the channel thickness should be around a third of the gate length. Improved short channel performance results in lower threshold voltage at the same OFF-current and hence higher gate overdrive voltage resulting in higher ON-current. Since FinFET is a quasi-planar device, ON-current per device footprint can be increased by making the fins taller and reducing the device footprint. Fin height was increased from 34 nm at 22-nm node to 42 nm at 14-nm node. Device footprint can be reduced by decreasing the fin pitch. The fin pitch was 60 nm at 22-nm node and was reduced to 42 nm at 14-nm node. According to the International Technology Roadmap for Semiconductors 2.0, the fin pitch, fin width, and gate length are expected to scale. The ratio of fin width to gate length is 1/3 till the “11/10” nm node. Fin width scaling may be limited to 6 nm due to processing challenges. At the “8/7” nm node, the fin width to gate length ratio increases to 0.43, which can degrade the short-channel performance of the device. With careful source–drain underlap doping design, the short channel performance of the device can be improved due to longer effective gate length [7]. The fin thickness requirement can be relaxed to be about one-half of the gate length for acceptable short-channel performance. While the introduction of underlaps improves the short-channel performance, it can increase the total resistance of the device due to the addition of the resistance of the lightly doped underlap regions. The overall performance of an underlap device is an optimization between the underlap region resistance and the decrease in the threshold voltage due to improved short-channel performance and the corresponding increase in the gate overdrive voltage. However, the gate all around (GAA) FET is one of the novel devices which further enables scaling without hindering the device performance.

Because of the low characteristic length and higher drive current, GAA MOSFETs can achieve higher packing density as compared to double gate (DG) MOSFETs [8–10]. Also GAA FET has excellent electrostatic control of the channel, robustness against SCEs, better scaling options, no floating body effect, larger equivalent number of gates, and ideal subthreshold swing as compared to other multiple gate MOSFETs. Hence, the GAA FET is a promising solution for nanoscale technology complementary metal–oxide–semiconductor (CMOS) devices [11–15]. Recently, MOS devices with sub-50 nm channel length demonstrate more than 100 GHz of cut-off frequency [16–18]. Important device parameters such as threshold voltage (Vth), ON-OFF ratio (ION/IOFF), SS and DIBL are very much sensitive to the device geometry such as channel length, channel thickness, and gate work function. In this paper, analysing the performance of underlap GAAFET and compare the electrical parameters of GAA FET with underlap GAA FET. In section 2 the device structure description that includes all the dimensions, materials and doping concentrations of both devices and in this section also analyses the physics of the device using device numerical simulations and models activated for simulation. Section 3 comprises all results and discussion. Finally, the concluding remarks are presented in section 4

II. DEVICE STRUCTURE

Fig. 1. shows the 3D schematic view of a) GAA FET and b) underlap GAA FET. Both the GAA FET devices are modelled and characterized by using Silvaco TCAD tools. The device has been simulated using 3D device simulator Silvaco TCAD. Device A is designed by wrapping the SiO2 layer on the channel and the oxide layer is surrounded by the gate metal, and Device B is developed by taking the Device A, extend the equal channel length on both sides of source/drain. Device B is a underlap GAA FET designed by extension of the channel region in source and drain side known as underlap region and the source & drain bulk makes bigger. Symmetrical distances are being adopted from source to gate and gate to drain (S-G and G-D) by fixing the gate length identical is cited as underlap. Here, the observation has been done for the underlap length of 2.5 nm. SiO2 layer is chosen as dielectric material in between the gate metal and substrate.

Lg is the channel length or gate length between source and drain and Wth is the channel width. Lus and Lud is the extension length of the source and drain. It decides the significant underlap capacitance and resistance of source or drain. Tox is gate oxide thickness. The underlap GAA FET structure can be characterized in terms of gate length (Lg) and underlap length (Lu). The silicon material with N-type source and drain doping concentration is 1×1018 cm-3 whereas P-type doping concentration of 1×1015 cm-3, and oxide thickness is 1 nm. The corresponding k value for gate dielectric material are 3.9. Table I shows the parameters used for the present work of simulation. The electrical parameters of the devices are simulated by using Silvaco Atlas simulator. In the simulation of the devices, the Shockley–Read–Hall (SRH) recombination using fixed lifetimes model, the band gap narrowing model, and Auger recombination models are also included for better modelling of the 22 nm gate length GAA FETs.

Table I: Device parameters

III. RESULT

Charge sharing is the main source for Vth roll-off. The Threshold voltage variations (Vth) for Device A and Device B are shown in Fig. 2(a). For Device B acquired higher threshold voltage then Device A. From the graph, it is observed that the threshold voltage of two devices is determined to be 0.278 V and 0.282 V, respectively, at a drain voltage of 0.1 V. The threshold voltage begins to reduce as the channel length is shortening in CMOS devices because depletion region charge is supported by source and drain. An increase in drain current is observed in the underlap device with an increase in drain voltage as the gate voltage is varied from 0 V to 1 V. For a drain voltage of 0.1 V, the maximum drain current for the device A is 19 µA/µm, while it is 21 µA/µm for the device B. A similar trend is also observed for increased drain voltages where the drain current for device B is 124.88 µA/µm when compared to 102.42 µA/µm for the device A at drain voltage of 1 V that are shown in Fig. 2(b). Hence, the rectangular GAA FET with underlap device holds an upper hand in respect to performance and switching speed as shown in Fig. 2(c).

IV. ACKNOWLEDGEMENT

The Authors are thankful to the HoD, Department of Electronics and Communication Engineering and also thanks to Chairman, Principal and management of Visakha Institute of Engineering and Technology, Visakhapatnam to carry out this research work

Conclusion

The simulation of GAA FET and underlap GAA FET devices for a gate length of 22 nm with symmetrical underlap was performed by using SILVACO ATLAS simulation software. In this paper, the electrical characteristics of two devices have been studied and analyzed. The simulation results precisely optimized inconsideration of threshold voltage (Vth), ON current (ION), ION/IOFF ratio, and slightly increased the OFF current (IOFF), sub threshold swing (SS), DIBL of simulated device. Increased ON current are found in underlap GAA FET comparing with GAA FET which increases the device speed and also enhanced the device performance due to improved current ratio.

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Copyright

Copyright © 2023 Jeevan Rao Batakala, Nukala Venkayya Aarya Lakshmi Vara Prasad, Mulagapaka Tarun, Ellapu Yagna Varahala Rao, Kalla Sandhya. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.